PROGRAMMING THE CORTEX-M MCU


 

Cortex-M MCU Architectures

The original Acorn Risc Machine CPU was designed to power follow-on PCs of the highly successful BBC Micro personal computers. Provided with “no budget” and with chip engineers who had no previous experience in custom CPU design, the engineers (primarily Steve Furber and Sophie Wilson) managed to invent an architecture that has a long-lasting impact in the computing world, especially in areas where high performance and low power are important criteria. The people and company that worked on the Acorn Risc Machine eventually formed a company named ARM. ARM does not make any actual chips, but rather licenses its IP to silicon vendors.

 

The ARM instruction set designs are influenced by RISC (Reduced Instruction Set Computer). However, RISC architecture purity is never a top-most priority in ARM designs.


The Cortex series is the latest evolution of the original ARM architecture, with much of the "DNA" still intact, particularly in the emphasis on simple and efficient designs. The Cortex-M variant is designed for embedded uses, and all major embedded silicon vendors license the cores and use them in their MCU offerings.

 

As the CPU cores used in the MCUs are the same, vendors differentiate their products by providing different I/O peripherals, package size and availability, performance of the flash memory, CPU speed, prices and other factors that the vendor can control.

 

The Cortex-M CPU executes the Thumb2 instruction set (ARM also has the Arm and Thumb instruction sets). Thumb2 provides the performance similar to the 32-bit only Arm instruction set, while being code size competitive with the 16-bit only Thumb instructions.

 

One of the design goals of the ARM Cortex architecture is to be able to write all code in a high- level language such as C, including system functions and interrupt handlers.

Major Cortex-M Variants

ARM uses two types of categories to refer to ARM chips: the architecture/ISA variants or versions, and the microarchitectures which refer to specific implementations of an architecture variant. The following is an incomplete table listing some of the Cortex-M MCU categories. ARMv6 runs 16-bit Thumb instructions only, while ARMv7 and ARMv8 run mixed 16/32-bit Thumb2 instructions.

 

Architecture Variant

Microarchitecture

Examples

Notes

ARMv6-M

Cortex-M0
Cortex M0+

STM32F0xx
LPC1000

Low cost, slow speed

ARMv7-M

Cortex-M3

STM32F1xx
STM32F2xx
LPC17xx

 

ARMv7E-M

Cortex-M4

SAM 4L

Cortex-M3 + DSP

 

Cortex-M4F

STM32F4xx

Cortex-M4 with single precision FPU

 

Cortex-M7

 

Double efficiency over Cortex-M4

 

Cortex-M7F

STM32F7xx

Cortex-M7 with FPU

ARMv8-M

Cortex-M23

SAM L10
SAM L11

Similar to Cortex-M0+ with integer divide

 

Cortex-M33

 

Conceptually similar to a cross of Cortex-M4 and Cortex-M23. Optional FPU

 

At the minimum, the compiler must know whether to generate either 16-bit only Thumb instructions (Cortex-M0) or mixed 16/32-bit Thumb2 instructions.