REXIS Hardware Requirements

·         Cortex-M MCUs that do not use the M0/M0+ core (the M0/M0+ core will be supported in a future release). An MCU must also have the NVIC (Nested Vectored Interrupt Controller) and the SysTick timer, which are available on all commercial Cortex-M MCUs, but are nominally optional for a Cortex-M MCU.

·         REXIS itself uses 10K bytes of code and less than 1 K bytes of SRAM. Each task requires at the minimum about 600 bytes of SRAM; e.g., an MCU with 10K bytes of SRAM should support a dozen tasks comfortably, depending on the actual tasks’ stack usage.